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Rtd FPGA35S6100HR Bedienungsanleitung Seite 13

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RTD Embedded Technologies, Inc. | www.rtd.com 13 FPGA35S6 User’s Manual
CN8: High Speed Digital I/O Connector
Connector CN8 provides 40 digital I/O lines, along with a +5V pin and ground pins. These signals are 3.3V tolerant. The signal names reflect
the signal names I n the Xilinx UCF file with the device pin out.
CN8 is attached to Bank 1, and supports any of the Spartan 6 I/O Standards that use a 3.3V V
CCO
and no reference voltage. This includes
LVTTL, LVCMOS33 input and output, and LVDS_33 input. LVDS output is not supported in Bank 1.
Table 5: CN8 I/O Pin Assignments
Port2_n[0]
2
1
Port2_p[0]
Port2_n[1]
4
3
Port2_p[1]
Port2_n[2]
6
5
Port2_p[2]
Port2_n[3]
8
7
Port2_p[3]
GND
10
9
GND
Port2_n[4]
12
11
Port2_p[4]
Port2_n[5]
14
13
Port2_p[5]
Port2_n[6]
16
15
Port2_p[6]
Port2_n[7]
18
17
Port2_p[7]
GND
20
19
GND
Port2_n[8]
22
21
Port2_p[8]
Port2_n[9]
24
23
Port2_p[9]
Port2_n[10]
26
25
Port2_p[10]
Port2_n[11]
28
27
Port2_p[11]
GND
30
29
GND
Port2_n[12]
32
31
Port2_p[12]
Port2_n[13]
34
33
Port2_p[13]
Port2_n[14]
36
35
Port2_p[14]
Port2_n[15]
38
37
Port2_p[15]
GND
40
39
GND
Port2_n[16]
42
41
Port2_p[16]
Port2_n[17]
44
43
Port2_p[17]
Port2_n[18]
46
45
Port2_p[18]
Port2_n[19]
48
47
Port2_p[19]
GND
50
49
+5V
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