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Rtd FPGA35S6100HR Bedienungsanleitung Seite 14

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RTD Embedded Technologies, Inc. | www.rtd.com 14 FPGA35S6 User’s Manual
CN4 & CN9: Digital I/O Connector
Connectors CN4 and CN9 each provide 24 digital I/O lines, along with a +5V pin and ground pins. All I/O have pull up/pull down resistors that
are controlled by jumper options, also shown in the table. These signals are 5V tolerant. The signal names reflect the signal names I n the
Xilinx UCF file with the device pin out.
CN4 and CN9 are attached to Bank 2 and 0 respectively, and support any of the Spartan 6 I/O Standards that use a 3.3V V
CCO
and no
reference voltage. This includes LVTTL, LVCMOS33, and LVDS_33 input and output.
Table 6: CN4 I/O Pin Assignments
GND
2
1
port0_p[0]
JP1
GND
4
3
port0_n[0]
GND
6
5
port0_p[1]
GND
8
7
port0_n[1]
GND
10
9
port0_p[2]
GND
12
11
port0_n[2]
GND
14
13
port0_p[3]
GND
16
15
port0_n[3]
GND
18
17
port0_p[4]
JP2
GND
20
19
port0_n[4]
GND
22
21
port0_p[5]
GND
24
23
port0_n[5]
GND
26
25
port0_p[6]
GND
28
27
port0_n[6]
GND
30
29
port0_p[7]
GND
32
31
port0_n[7]
GND
34
33
port0_p[8]
JP3
GND
36
35
port0_n[8]
GND
38
37
port0_p[9]
GND
40
39
port0_n[9]
GND
42
41
port0_p[10]
GND
44
43
port0_n[10]
GND
46
45
port0_p[11]
GND
48
47
port0_n[11]
GND
50
49
+5V
Table 7: CN9 I/O Pin Assignments
GND
2
1
port1_p[0]
JP4
GND
4
3
port1_n[0]
GND
6
5
port1_p[1]
GND
8
7
port1_n[1]
GND
10
9
port1_p[2]
GND
12
11
port1_n[2]
GND
14
13
port1_p[3]
GND
16
15
port1_n[3]
GND
18
17
port1_p[4]
JP5
GND
20
19
port1_n[4]
GND
22
21
port1_p[5]
GND
24
23
port1_n[5]
GND
26
25
port1_p[6]
GND
28
27
port1_n[6]
GND
30
29
port1_p[7]
GND
32
31
port1_n[7]
JP6
GND
34
33
port1_p[8]
GND
36
35
port1_n[8]
GND
38
37
port1_p[9]
GND
40
39
port1_n[9]
GND
42
41
port1_p[10]
GND
44
43
port1_n[10]
GND
46
45
port1_p[11]
GND
48
47
port1_n[11]
GND
50
49
+5V
3.3.2 BUS CONNECTORS
CN1 (Top) & CN2 (Bottom): PCIe Connector
The PCIe connector is the connection to the system CPU. The position and pin assignments are compliant with the PCI/104-Express
Specification. (See PC/104 Specifications on page 29)
The FPGA35S6 is a “Universal” board, and can connect to either a Type 1 or Type 2 PCIe/104 connector.
3.3.3 JUMPERS
JP1, JP2, JP3, JP4, JP5, & JP6: Pull up/Pull down Jumper
JP1, JP2, JP3, JP4, JP5, and JP6 are 3-pin two position jumpers that are used to set pull up or pull downs options on the I/O signal lines of
CN4 and C5. Refer to Table 6 and Table 7 to determine which I/O pins are effected by each jumper.
Table 8: Pull up/Pull down Jumper options
Setting
Description
1-2
I/O is pulled up to 3.3V or 5V (Set by B1 and B2)
2-3
I/O is pulled down to GND
No Jumper
I/O has no pull up/pull down
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